FIG. 2 diagrammatically depicts a conventional transistor structure, which is oriented at a substrate surface 10 of a semiconductor substrate 1, for integrated circuits. The transistor structure is a field-effect transistor with two source/drain regions 31, 32 formed as doped regions beneath the substrate surface 10 in the semiconductor substrate 1. The two source/drain regions 31, 32 are spaced apart from one another by a channel region 33, which is either not doped or is doped by a conductivity type opposite the conductivity type of the source/drain regions 31, 32. A gate dielectric 21 is provided on the substrate surface 10 substantially above the channel region 33. A base portion 22, a highly conductive portion 23, and an insulator portion 24 of a gate conductor structure 2 adjoin the gate dielectric 21 in a vertical direction with respect to the substrate surface 10. The gate conductor structure 2 is surrounded by gate stack spacers 26 at side walls 20 oriented vertically with respect to the substrate surface 10.
The gate conductor structure 2 is produced during a lithographic process by patterning of a layer stack formed from the material of the base portion 22, the conductive material of the highly conductive portion 23, and the insulator material of the insulator portion 24. In this example, the material of the base portion is polysilicon. A width of the gate conductor structure 2 can correspond to a minimum feature size F, which is predetermined by the manufacturing process. In this context, the minimum feature size F denotes the width of the smallest lithography resolution unit. The gate stack spacers 26 are produced from a sublithographic process, for example, by non-isotropic etchback of a conformally deposited spacer material.
If the transistor structure is used to isolate a structure adjoining a first source/drain region, with the minimum possible leakage current over a prolonged period of time and to occasionally connect the structure to a driver or data line connected to the second source/drain region 32, the side walls 20 of the gate conductor structures 2 at least in the base portion 22 are subject to an oxidation process. This produces dielectric side wall oxides 25 at the side walls 20 in the region of the base portion 22. Incorporation of oxygen causes the base portions 22 to thicken. Since the oxide grows relatively more quickly along an existing oxide layer, gate dielectric portions 27, which thicken outward, for example, in the shape of a wedge in the direction of the side walls 20 or the source/drain regions 31, 32, also referred to below as bird's beak structures 27, are formed between the base portion 22 and the gate dielectric 21 below. The side wall structures 25 and the bird's beak structures 27 reduce a leakage current between the source/drain regions 31, 32 to the gate conductor structure 2 and a leakage current brought about by the GIDL (gate induced drain leakage) effect.
The oxidation process reduces the gate dielectric 21 by an amount 2* Δx due to oxidation of the side wall oxides 25 and by an amount 2* Δy as a result of the bird's beak structures 27. The effective channel width of the transistor structure illustrated is CL1. An overlap between the gate dielectric 21, including the bird's beak structures 27, and the source/drain regions 31, 32 is Ü1.
In the off state of the transistor structure, the source/drain regions 31, 32 are isolated from one another. A conductive channel between the two source/drain regions 31, 32, which bridges the channel region 33, is formed in a portion of the semiconductor substrate 1 which adjoins the gate conductor dielectric 21 by a potential at the conductive portions of the gate conductive structure 2.
Transistor structures, which can temporarily isolate an insulated structure connected to one of their two source/drain regions at a very low leakage current include, for example, transistors in the hold elements of A/D converters and select transistors of dynamic memory cells. Memory cells of dynamic random access memories (DRAMs) in each case can include a storage capacitor for storing an electric charge, which is characteristic of a data content of the memory cell, and a select transistor for addressing the storage capacitor. The storage capacitor is the structure to be isolated. One electrode (storage electrode) is connected to the first source/drain region of the select transistor.
In the case of trench capacitors, the storage capacitor is formed within the semiconductor substrate beneath the substrate surface. The select transistors are formed next to one another along the substrate surface of the semiconductor substrate. The source/drain regions and the channel region are provided as doped regions in the semiconductor substrate. The gate dielectric and a gate conductor structure are arranged above the substrate surface in the region of the channel region.
FIG. 1 illustrates a portion of a cell array 81 of a DRAM that is formed from a plurality of memory cells 8. In the cell array 81, the memory cells 8 are arranged in cell rows 82 and cell columns 83 that are orthogonal to the cell rows 82. FIG. 1 illustrates four cell rows 82 in cross section. Each memory cell includes a storage capacitor 4 and a select transistor 3. The memory cells 8 of adjacent cell rows 82 are offset with respect to one another by half the distance between memory cells. FIG. 1 illustrates two memory cells 8 in cross section.
The memory cells 8 are oriented to a trench 41 introduced into a semiconductor substrate 1 from a substrate surface 10. The trench 41 is lined with a capacitor dielectric 44 in a lower portion and with a collar insulator 45 in an upper portion. The capacitor dielectric 44 isolates a storage electrode 42 provided in the interior of the trench 41 as a filling. The filling includes a conductive semiconductor material, counterelectrode 43, is formed as a doped region in the semiconductor substrate 1 surrounding the trench 41 in a lower portion. The collar insulator 45 insulates the storage electrode 42 from an upper portion of the semiconductor substrate 1, in which source/drain regions 31, 32 of the select transistor 3 are formed.
The two source/drain regions 31, 32 of the select transistor 3 are spaced apart from one another by a channel region 33. A gate dielectric 21 is formed above the channel region 33. The gate conductor structure 2 adjoins the gate dielectric 21 in a direction which is vertical with respect to the substrate surface 10. The gate conductor structure 2 includes a base portion 22, which adjoins the gate dielectric 21, a highly conductive portion 23, which adjoins the base portion 22, and an insulator portion 24, which is a covering. Side wall oxides 25 are provided at the side walls 20 of the gate conductor structure 2 in the base portion 22. The gate dielectric 21 includes bird's beak structures 27. In the region of a buried strap window 46, the storage electrode 42 adjoins a buried strap outdiffusion 48, which connects to a first source/drain region 31 of the select transistor 3 respectively assigned to the storage capacitor 4. The storage electrode 42 is isolated from the adjacent memory cell 8′ by a shallow insulator structure 6 (STI, shallow trench isolation).
The select transistors 3 or gate conductor structures 2, which are grouped together to form a cell row 82, are connected to one another and form address or word lines 53 running parallel to the cell row 82. When the memory device is operating, the word lines 53 are driven by logic arranged outside the cell array 81 so as to address memory cells 8. Bit or data lines 5, which are connected to the second source/drain region 32 of the select transistor 3 via data line contacts 51, are arranged transversely with respect to the word lines 53 formed by the gate conductor structures 2 arranged next to one another and adjoining one another. A covering oxide (i.e., TTO, trench top oxide) 47 insulates the storage electrode 42 from the respectively passing, inactive word line 53 or gate conductor structure 2.
In general terms, it is desired to reduce the size of transistor structures without any adverse effect on functionality. In the case of planar transistor structures, smaller feature sizes lead to shorter distances between the two source/drain regions of the transistor structure and to shorter channel lengths of a channel formed in the channel region between the two source/drain regions. However, with minimum feature sizes of less than 100 nanometers, a shortening of the channel length corresponding to a reduction in the minimum feature size leads to disproportionately greater difficulties in connection with a lower storage voltage then being required and/or with realizing a suitable doping profile of the channel region.
When reducing the size of memory cells having a storage capacitor and a select transistor, it is generally aimed to minimize leakage currents flowing away from the storage electrode for predetermined horizontal dimensions.
A transistor structure with a leakage current from a storage structure, which is to be isolated and connected to one of the source/drain regions of the transistor structure, which is reduced compared to known transistor structures for the same dimensions is desirable. Furthermore, a memory cell with a low leakage current, a DRAM and a method for fabricating a transistor structure of this type is desirable.